DATE 2027 Technical Programme Committee

TPC chairs and members can update their personnel data like affiliation in SoftConf only. Please update your data in your SoftConf Profile. This page is updated automatically each full hour.

Track D: Design Methods and Tools

addresses design automation, design tools, and Hardware architectures for electronic and embedded systems. The emphasis is on methods, algorithms, and tools related to the use of computers in designing complete and complex systems. The track’s focus includes significant improvements on existing design methods and tools, as well as forward-looking approaches to model and design future system architectures and design flows.

Topics
Click on the topic title to find further details.

Letícia Maria Bolzani Pöhls, IHP - Leibniz Institute for High Performance Microelectronics, DED-Track Co-Chair
Letícia Maria Bolzani Pöhls, IHP - Leibniz Institute for High Performance Microelectronics, DE
leticia@poehls.com

Graziano Pravadelli, University of Verona, ITD-Track Co-Chair
Graziano Pravadelli, University of Verona, IT
graziano.pravadelli@univr.it

Track A: Application Design

is devoted to the presentation and discussion of design experiences with a high degree of industrial relevance, real-world implementations, and applications of specific design and test methodologies. Contributions should illustrate innovative or record-breaking design and test methodologies, which shall provide viable solutions in tomorrow’s silicon, embedded systems, and large-scale Systems.

Topics
Click on the topic title to find further details.

Ioana Vataleju, TIMA/CNRS/Université de Grenoble-Alpes, FRA-Track Chair
Ioana Vataleju, TIMA/CNRS/Université de Grenoble-Alpes, FR
ioana.vatajelu@univ-grenoble-alpes.fr

Track T: Test and Dependability

covers all test, design-for-test, reliability, and design-for-robustness issues, at system-, chip-, circuit-, and device-level for both analogue and digital electronics. Topics of interest also include diagnosis, failure mode analysis, debug and post-silicon Validation challenges, and test and fault injection methods addressing system security.

Topics
Click on the topic title to find further details.

Marcello Traiola, Inria, FRT-Track Chair
Marcello Traiola, Inria, FR
marcello.traiola@inria.fr

Track E: Embedded Systems Design

is devoted to the modelling, analysis, design, verification and deployment of embedded software or embedded/cyber-physical systems. Areas of interest include methods, tools, methodologies and development environments for real-time systems, cyber-physical systems, networked systems, and dependable systems. Emphasis is also on model-based design and verification, embedded software platforms, software compilation and integration for these systems.

Topics
Click on the topic title to find further details.

Nele Mentens, KU Leuven, BE | Leiden University, NLE-Track Chair
Nele Mentens, KU Leuven, BE | Leiden University, NL
nele.mentens@kuleuven.be

Topics per Track

Track D: Design Methods and Tools

D1 System-level design methodologies and high-level synthesis

This topic focuses on methodologies and tools for system-level design and high-level synthesis (HLS), enabling the efficient development of complex hardware and hardware/software systems. It encompasses advanced techniques for translating high-level and behavioural descriptions into optimized hardware architectures, supporting both productivity and performance.
Areas of interest include high-level and system-level synthesis approaches, high-level programming languages and models for system specification and optimization, and methods for hardware/software co-design and partitioning. Contributions related to the synthesis of communication protocols and hardware/software interfaces, interface-based design, and correct-by-construction methodologies are highly encouraged. We also welcome works on control and data flow analysis, high-level scheduling, resource allocation, and binding techniques. The topic covers design space exploration strategies and systematic optimization techniques targeting both HLS and system-level design. Platform-based design approaches, IP reuse strategies, and the development of accelerator-rich architectures are particularly relevant, as are hardware/software design patterns for multi-processor systems-on-chip (MPSoCs) and heterogeneous computing platforms. Finally, we encourage to demonstrate how these system-level design and high-level synthesis methodologies apply to emerging domains, with a particular emphasis on machine learning and other compute-intensive applications.

Chair: Benjamin Carrion Schaefer, The University of Texas at Dallas, US

Co-Chair: Sharad Sinha, Indian Institute of Technology (IIT) Goa, IN

Topic Members

  • Jason H. Anderson, University of Toronto, CA
  • Yao Chen, National University of Singapore, SG
  • Steve Dai, NVIDIA, US
  • Steven Derrien, Université de Bretagne Occidentale/Lab-STICC, FR
  • Zhenman Fang, Simon Fraser University, CA
  • Chandan Karfa, Indian Institute of Technology Guwahati, IN
  • He Li, Southeast University, CN
  • Yingjie Li, Simon Fraser University, CA
  • Zhe Lin, Sun Yat-sen University, CN
  • Christian Pilato, Politecnico di Milano, IT
  • Simon Rokicki, Irisa, FR
  • Siva Satyendra Sahoo, IMEC, BE
  • Souradip Sarkar, Synopsys, DE
  • Biruk Seyoum, Columbia University, US
  • Bindiya T S, National Institute of Technology Calicut, IN
  • Nan Wu, George Washington University, US
  • Hanchen Ye, Apple, US
  • Jie Zhang, Zhejiang University, CN
  • Wei Zhang, Hong Kong University of Science and Technology, HK
  • Kang Zhao, Beijing University of Posts and Telecommunications, CN

D2 System simulation and validation

This topic addresses simulation-based and semi-formal methods for the validation and verification of complex digital systems, including systems-on-chip (SoCs), cyber-physical systems, and emerging computing architectures. Contributions are invited at all levels of abstraction—from system-level down to the circuit level—with a focus on methodologies that enhance correctness, reliability, and security. Key areas include the generation and qualification of testbenches and assertions, the development and application of functional coverage metrics, and techniques for checker synthesis and optimization. We welcome submissions exploring acceleration-driven and emulation-based approaches for efficient verification, as well as simulation-based methods for pre- and post-silicon validation and debugging.
The topic also encompasses verification and validation strategies tailored to modern application domains such as the Internet of Things (IoT) and cloud infrastructures. We also invite contributions to verify non-functional requirements, such as validation of security and reliability, including the detection of vulnerabilities, with or without the integration of artificial intelligence and machine learning techniques. Note that submissions focused on the simulation of analogue circuits should be directed to topic DT4.

Chair: Pierluigi Nuzzo, University of California, Berkeley, US

Co-Chair: Samuele Germiniani, University of Guglielmo Marconi, IT

Topic Members

  • Ansuman Banerjee, Indian Statistical Institute, IN
  • Nicola Dall'Ora, University of Verona, IT
  • Thao Dang, CNRS/VERIMAG, FR
  • Keerthikumara Devarajegowda, Siemens EDA, DE
  • Subhajit Dutta Chowdhury, AMD, US
  • Wolfgang Ecker, Infineon Technologies, DE
  • Kerstin Eder, University of Bristol, GB
  • Mohammad R. Fadiheh, RPTU Kaiserslautern, DE
  • Goerschwin Fey, Hamburg University of Technology, DE
  • Ramesh Karri, NYU, US
  • Vikash Kumar, ARM, US
  • Huaixi Lu, Amazon Web Services, US
  • Yangdi Lyu, Hong Kong University of Science and Technology (Guangzhou), CN
  • Gianluca Martino, Lawrence Berkeley National Laboratory, US
  • Nikhil Naik, RTX Technology Research Center, US
  • Debjit Pal, University of Illinois at Chicago, US
  • Loganath Ramachandran, Verikwest Systems Inc, US
  • Sara Vinco, Politecnico di Torino, IT
  • Lennart Weingarten, University of Bremen, DE
  • Yue Xing, Princeton University, US
  • Takahide Yoshikawa, Fujitsu, JP
  • Marcela Zachariasova, Brno University of Technology, CZ
  • Hao Zheng, University of South Florida, US
  • Keren Zhu, Fudan University, CN

D3 Formal methods and verification

This topic focuses on the use of formal methods for the modelling, specification, and verification of hardware, software, and integrated hardware/software systems. It covers rigorous techniques that ensure functional correctness, safety, and reliability across a wide range of platforms, from IP blocks and SoCs to complete systems and emerging computing paradigms. Relevant areas include the development and application of formal models, as well as verification techniques such as equivalence checking, model checking, symbolic simulation, theorem proving, abstraction, and compositional reasoning. The topic also emphasizes advances in core algorithmic technologies supporting formal verification, particularly those based on SAT and SMT solving.
We welcome contributions on the formal verification of hardware components (including IPs, cores, and systems-on-chip), embedded software, and cyber-physical or hybrid systems with timing constraints. Additional points of interest include formal synthesis, the integration of formal techniques into mainstream design flows, and the specific challenges posed by multi-core systems, both as verification targets and as platforms for executing formal verification tools.
This topic also encourages work on the application of formal methods to emerging technologies, where correctness and trustworthiness are critical.

Chair: Stefano Quer, Politecnico di Torino, IT

Co-Chair: Ivana Černá, Masaryk University, CZ

Topic Members

  • Anna Bernasconi, Universita' di Pisa, IT
  • Alessandro Cimatti, Fondazione Bruno Kessler, IT
  • Pallab Dasgupta, Synopsys, US
  • Luca Geretti, University of Verona, IT
  • Daniel Grosse, Johannes Kepler University Linz, AT
  • Dilian Gurov, KTH Royal Institute of Technology, SE
  • Ahmed Irfan, Code Metal, US
  • Chandan Kumar Jha, University of Bremen, DE
  • Muhammed Luqman Jukaku, synopsys.com, US
  • Rune Krauss, DFKI, DE
  • Ulrich Kühne, Télécom Paris, Institut polytechnique de Paris, FR
  • Nicola Nicolici, McMaster University, CA
  • Disha Puri, Director R&D, IN
  • Christoph Scholl, University Freiburg, DE
  • Anna Slobodova, Arm, US
  • Hongce Zhang, Hong Kong University of Science and Technology (Guangzhou), CN

DT4 Design and test for analogue and mixed-signal circuits and systems, and MEMS

Analogue, radio-frequency, mixed-signal, MEMS, circuit and system synthesis and optimization; layout and parasitic-aware synthesis; design for manufacturability, yield, reliability; analysis of variability effects; performance modelling; formal, numerical and symbolic simulation methods; topology generation; HW description languages and models of computation; self-healing and self-calibration; test generation, built-in self-test and design for testability; fault modelling, diagnosis and simulation; defect characterization and failure analysis; on-line test and fault tolerance; test metrics.

Chair: Ricardo Martins, Instituto de Telecomunicações / Instituto Superior Técnico – Universidade de Lisboa, PT

Co-Chair: Salvador Mir, CNRS/Univ. Grenoble Alpes/TIMA, FR

Topic Members

  • Martin Andraud, UCLouvain, BE
  • Tiago Balen, UFRGS, BR
  • Manuel Barragan, TIMA Laboratory, FR
  • Hung-Ming Chen, Institute of Electronics, National Yang Ming Chiao Tung University, TW
  • Chenhao Chu, ETH Zurich, CH
  • William Eisenstadt, University of Florida, US
  • Renato Feitoza, PROPHESEE, FR
  • Husni Habal, Infineon Technologies AG, DE
  • Lida Kouhalvandi, Dogus university, TR
  • Yolanda Lechuga, University of Cantabria, ES
  • Piero Malcovati, University of Pavia, IT
  • Juho Park, Princeton Univerrsity, US
  • Fabio Passos, University of Lisbon and INESC-ID, PT
  • Elisenda Roca, Instituto de Microelectronica de Sevilla, ES
  • Rosa Rodríguez-Montañés, UPC, ES
  • Armin Tajalli, University of Utah, US
  • Yasuhiro Takashima, University of Kitakyushu, JP

DT5 Design and test of hardware security primitives

Hardware security primitives, including classical and post-quantum cryptographic circuits, multiparty computation (MPC), zero-knowledge proof systems, homomorphic encryption; side-channel countermeasure primitives and analysis (including modelling, verification, and simulation); fault injection countermeasures and attacks; physically unclonable functions (PUF) and true random number generators (TRNG); hardware trojan primitives; AI methods in hardware security; AI accelerators and their relevant physical attacks and countermeasures; nano security primitives.

Chair: Paolo Maistri, TIMA Laboratory, FR

Co-Chair: Lukasz Chmielewski, Masaryk University (Brno, Czechia), CZ

Topic Members

  • Aydin Aysu, North Carolina State University, US
  • Gaëtan Cassiers, UCLouvain, BE
  • Elke De Mulder, Google, US
  • Wieland Fischer, Infineon Technologies, DE
  • Sylvain Guilley, Secure-IC, FR
  • Xiaolu Hou, Nanyang Technological University, SG
  • Tuba Kiyan, Technische Universität Berlin, DE
  • Maurizio Martina, Politecnico di Torino, IT
  • Philippe Maurine, University of Montpellier, FR
  • Silvia Mella, Radboud University, NL
  • Athanasios Papadimitriou, Department of Digital Systems, University of the Peloponnese, GR
  • Michael Pehl, Technical University of Munich, DE
  • Marta Portela-Garcia, Universidad Carlos III de Madrid, ES
  • Markku-Juhani Saarinen, Tampere University, FI
  • Julian Speith, Max Planck Institute for Security and Privacy (MPI-SP), DE
  • Dilara Toprakhisar, KU Leuven, BE
  • Rei Ueno, Kyoto University, JP
  • Praveen Vadnala, PQShield BV, NL
  • Emanuele Valea, CEA LIST, FR
  • Raphael Viera, Mines Saint-Etienne, FR
  • Srinivas Vivek, IIIT Bangalore, IN

DT6 Design and test of secure systems

Design-for-trust (secure design methods); Test infrastructures for secure devices; Trusted manufacturing; Counterfeit detection and avoidance; Design, test and automation (for HW tampering attacks and protection, for Countermeasures, for Side-channel protection verification, for Fault protection verification); Microarchitectural attacks; HW trojans (attacks, detection, or countermeasures); Machine learning for the above topics, Side-channel attacks on machine learning and counter measures.

Chair: Tobias Schneider, NXP Semiconductors, AT

Co-Chair: Ileana Buhan, Radboud University, NL

Topic Members

  • Anita Aghaie, Siemens AG, DE
  • Tolga Arul, Barkhausen Institut, DE
  • Jakub Breier, TTControl GmbH, AT
  • Anupam Chattopadhyay, Nanyang Technological University, SG
  • Ricardo Chaves, INESC-ID, IST, Universidade de Lisboa, PT
  • Giorgio Di Natale, TIMA - CNRS, FR
  • Nisha Jacob Kabakci, Fraunhofer AISEC, DE
  • Dirmanto Jap, Temasek Laboratories @NTU, SG
  • Dina Kamel, Universit� catholique de Louvain, BE
  • ayesha khalid, Queen's University Belfast, GB
  • Johann Knechtel, New York University Abu Dhabi, AE
  • Georg Land, Intel, DE
  • Vianney Lapotre, Univ. Bretagne Sud, UMR CNRS 6285, Lab-STICC, FR
  • Itamar Levi, Faculty of Engineering, Bar-Ilan University, IL
  • Soundes Marzougui, Qubit Guard, DE
  • David Oswald, Durham University, GB
  • Kostas Papagiannopoulos, University of Amsterdam, NL
  • Francesco Regazzoni, University of Amsterdam and Università della Svizzera italiana, CH
  • Aein Rezaei Shahmirzadi, PQShield, DE
  • Junko Takahashi, NTT Social Informatics Laboratories, JP
  • Lichao Wu, University of Bristol, GB

D7 Network on chip and on-chip communication

This topic covers the architecture, design methodologies, and modelling and simulation techniques for intra- and inter-chip interconnects, with a focus on network-on-chip (NoC) and general on-chip communication infrastructures. Contributions are encouraged in all aspects of NoC and interconnect design, including topology exploration, router microarchitecture, interface design, flow control mechanisms, quality of service (QoS), security, reliability, and performance optimization.
The topic welcomes work on design space exploration frameworks, communication-centric design approaches, and programming models or specifications tailored to on-chip communication. Submissions that address challenges posed by emerging technology constraints—such as designs targeting FPGAs, chiplet-based or interposer-based 2.5D and 3D integration, photonic interconnects, wireless NoCs, or non-volatile memory technologies—are particularly relevant.
We also invite contributions from application-driven perspectives, especially those focusing on interconnect solutions for high-performance computing, in-memory or near-memory computing architectures, and communication support for machine learning and artificial intelligence accelerators.

Chair: Davide Bertozzi, University of Manchester, GB

Co-Chair: Josè Flich, Associate Professor, Universitat Politècnica de València, ES

Topic Members

  • Marco Balboni, SiFive, IT
  • Sujay Deb, IIIT Delhi, IN
  • Giorgos Dimitrakopoulos, Democritus University of Thrace, GR
  • Carles Hernandez, Universitat Politecnica de Valencia, ES
  • Avinash Karanth, Ohio University, US
  • Cedric Killian, Universite Jean Monnet, FR
  • Zhonghai Lu, The Hongkong University of Science and Technology (Guangzhou), CN
  • Hiroki Matsutani, Keio University, JP
  • Sudeep Pasricha, Colorado State University, US
  • Samuel Rodrigo Mocholi, NUMASCALE, ES

D8 Architectural and microarchitectural design

This topic seeks innovative contributions in architectural and microarchitectural design for modern computing systems, with a particular focus on addressing key challenges related to performance, energy efficiency, scalability, and predictability. Within the architectural domain, we welcome work on the design and extension of instruction set architectures (ISA), memory system organization, and architectural mechanisms supporting concurrency and parallelism. The topic also covers multi-core and many-core architectures, application-specific architectures and domain-specific accelerators, as well as system-level architectures and architectural support for real-time and time-predictable execution. In the microarchitectural domain, we invite submissions addressing core microarchitecture design, including techniques for instruction fetch, branch prediction, and decoding, as well as register file and execution unit design. Contributions focusing on memory-related microarchitectural optimizations—such as cache hierarchy design and load/store management—are particularly relevant. Additionally, we encourage work that explores microarchitectural strategies for timing predictability and real-time constraints.
Overall, this topic places strong emphasis on innovative hardware design techniques tailored to the demands of emerging and compute-intensive workloads, including artificial intelligence, machine learning, edge and cloud computing, and autonomous systems.

Topic Members

    D9 Low-power, energy-efficient and thermal-aware design

    This topic focuses on theories, tools, methodologies and circuit-level structures to implement electronic circuits and systems with low power consumption, high energy efficiency, and correct thermal behaviour. These can be applied to a full range of scales, from ultra-low power systems (e.g. for portable/wearable applications at the edge of the IoT) to large-scale battery systems (electric vehicles, energy storage systems) and high-performance systems (data-centres and cloud computing).
    Topics of interest include: low-power digital circuits and systems, energy-aware system design, battery-aware system design, including energy efficiency optimization for application specific designs (e.g. AI, ML, etc.); smart management of heterogeneous energy-sources; energy harvesting for cyber-physical systems; hardware/software cross-layer optimizations, with emphasis on power modelling and optimization; thermal/power monitors and knobs at circuit level; temperature modelling and prediction; thermal-power-aware optimization; thermal management for chiplets, multi-chiplet, and heterogeneous packaging; power and thermal modelling for 2.5D/3D architectures; advanced thermal simulation methodology for large-scale HPC systems; thermal-aware design for AI chips.

    Chair: Massimo Poncino, Politecnico di Torino, IT

    Co-Chair: Grace Li Zhang, TU Darmstadt, DE

    Topic Members

    • Ganapati Bhat, Washington State University, US
    • Tinghuan Chen, The Chinese University of Hong Kong, Shenzhen, CN
    • Yu-Guang Chen, National Central University, TW
    • Yukai Chen, IMEC, BE
    • Stefano Cherubin, NTNU, NO
    • Georg Gläser, IMMS Institut für Mikroelektronik- und Mechatronik-Systeme gemeinnützige GmbH, DE
    • Iris Hui-Ru Jiang, National Taiwan University, TW
    • Chang Meng, Eindhoven University of Technology, NL
    • Ying Zhu, China Information Communication Technologies Gro, CN

    D10 Approximate computing

    This topic focuses on design techniques and methodologies for approximate computing across all levels of the computing stack, from circuits to software.
    We invite contributions on circuit-level and architectural-level approximation, as well as techniques applied at the memory, operating system, and software layers. Both top-down and bottom-up approaches are of interest, including the design and use of finite precision arithmetic, inexact or approximate operators, and stochastic computing architectures.
    The topic also encompasses cross-layer approximation strategies, where trade-offs are coordinated across multiple abstraction levels. Relevant areas include dynamic approximation techniques, quality assessment and metrics for approximate systems, and design automation tools that support the modelling, synthesis, and benchmarking of approximate computing systems.
    We particularly encourage submissions that demonstrate systematic and principled methods for approximation, and that address real-world use cases or integrate approximation into broader system-level design flows.

    Chair: Jie Han, University of Alberta, CA

    Co-Chair: Laura Pozzi, USI Lugano, CH

    Topic Members

    • Muhammad Awais, Paderborn University, DE
    • Salvatore Barone, Pegaso University, IT
    • Alberto Antonio Del Barrio Garcia, Complutense University of Madrid, ES
    • Zahra Ebrahimi, Ruhr University Bochum, DE
    • Silviu-Ioan Filip, Inria, FR
    • Georgios Karakonstantis, University of Thessaly, GR
    • Alexandra Kourfali, EuroHPC Joint Undertaking, LU
    • Siting Liu, ShanghaiTech University, CN
    • Weiqiang Liu, Nanjing University of Aeronautics and Astronautics, CN
    • Akul Malhotra, IBM Research, US
    • Ettore Napoli, University of Salerno - DIEM, IT
    • Weikang Qian, Shanghai Jiao Tong University, CN
    • Alessandro Savino, Politecnico di Torino, IT
    • Zdenek Vasicek, Brno University of Technology, CZ
    • Lei Zhang, University of Regina, CA
    • Tingting Zhang, Nanjing University of Aeronautics and Astronautics, CN

    D11 Reconfigurable computing

    The topic focuses on reconfigurable designs, systems, applications, methods, and tools. We welcome contributions on reconfigurable architectures and technologies (e.g., fine-grain and coarse-grain devices); reconfigurable application acceleration and energy efficiency; programming models and runtime systems for reconfigurable platforms; design methods, tools, and frameworks for reconfigurable systems; dynamic and partial reconfiguration techniques; and emerging applications of reconfigurable computing.

    Chair: Ioannis Sourdis, Chalmers University of Technology, SE

    Co-Chair: Bokyung Kim, NC State University, US

    Topic Members

    • Amila Akagic, University of Sarajevo, BA
    • João Cardoso, University of Porto, PT
    • Luigi Carro, UFRGS, BR
    • Young-kyu Choi, Inha University, KR
    • Grigorios Chrysos, Technical University of Crete, GR
    • Catalin Bogdan Ciobanu, Transilvania University of Brasov, RO
    • Maya Gokhale, LLNL, US
    • Konstantina Koliogeorgi, ETH, CH
    • Ioannis Papaefstathiou, Aristotle University of Thessaloniki, GR
    • Marco D. Santambrogio, Politecnico di Milano, IT
    • Dirk Stroobandt, Ghent University, BE
    • Christos Strydis, Erasmus Medical Center & Delft University of Technology, NL
    • Dimitris Theodoropoulos, Institute of Communication and Computer Systems, GR

    D12 Logical analysis and design

    The topic solicits cutting-edge contributions in, but not limited to, the following areas: Combinational and sequential synthesis for integrated circuits; data structures for synthesis; technology mapping; power-, performance- and/or area-driven synthesis; logic synthesis for emerging technologies; methods for FSM optimization, synthesis and analysis; FPGA synthesis; arithmetic circuit synthesis and optimization; logic ECO (engineering change order); logic synthesis utilizing AI/ML techniques; interaction between logic synthesis and physical design.

    Chair: Jie-Hong Roland Jiang, National Taiwan University, TW

    Co-Chair: Petr Fiser, Czech Technical University in Prague, FIT, CZ

    Topic Members

    • Zhufei Chu, Ningbo University, CN
    • Winston Haaswijk, Cadence Design Systems, NL
    • Timothy Kam, Intel, US
    • Natalia Kushik, Télécom SudParis, FR
    • Walter Lau Neto, Synopsys Inc, US
    • Siang-Yun Lee, Cadence Design Systems, DE
    • Yukio Miyasaka, ETHZ, CH
    • Andre Reis, UFRGS, BR
    • Heinz Riener, Cadence Design Systems, DE
    • Tsutomu Sasao, Meiji University, JP
    • Eleonora Testa, Synopsys Inc, US
    • Tiziano Villa, Universita' di Verona, IT

    D13 Physical analysis and design

    Statistical timing analysis and closure; asynchronous and mixed synchronous/asynchronous circuits; floorplanning; automated place-and-route; interconnect- and performance-driven layout; process technology developments; parasitic and variation-aware extraction for on-chip interconnect and passives; macro-modelling, behavioural and reduced order modelling; modelling and analysis of noise due to electromagnetic interaction of signal, power/ground, and substrate.

    Topic Members

      D14 Emerging design technologies for future computing

      The topic includes modelling, circuit design, HW/SW co-design, and design automation flows for future computing, including but not limited to: logic devices based on emerging technologies (e.g., spintronics, ferroelectrics, 2D materials, tunnel transistors, coupled oscillators, NEMS, etc.); alternative interconnect technologies (e.g., optical, RF, 3D, 2D materials, spintronics, etc.); monolithic 3D integration (including TSV modelling and design space exploration, etc.); memory-centric and disaggregated architectures based on new technologies enabled by protocols such as CXL, including pooled/shared memory design and HW/SW co-design for coherent interconnects.

      Chair: Michael Niemier, University of Notre Dame, US

      Co-Chair: Hassan AZIZA, Aix-Marseille Université, FR

      Topic Members

      • Sergi Abadal, N3Cat at Universitat Politecnica de Catalunya (UPC), ES
      • Iris Bahar, Colorado School of Mines, US
      • Nicoleta Cucu Laurenciu, Radboud University, NL
      • Abhijit Das, Indian Institute of Technology Hyderabad, IN
      • Swaroop Ghosh, Pennsylvania State University, US
      • Jiaqi Gu, Arizona State University, US
      • Edward Jones, University of Manchester, GB
      • Asif Ali Khan, TU Dresden, DE
      • Haitong Li, Purdue University, US
      • Xueqing Li, Tsinghua University, CN
      • Dayane Reis, University of South Florida, US
      • Tommaso Rizzi, IHP - Leibniz Institute for High Performance Microelectronics, DE
      • Theofilos Spyrou, Delft University of Technology, NL
      • Luca Sterpone, Politecnico di Torino, IT
      • Bonan Yan, Peking University, CN
      • Marina Zapater, University of Applied Sciences Western Switzerland (HES-SO), CH

      D15 Emerging design technologies for future memories

      The topic focuses on novel modelling, circuit and architecture design, and EDA methodologies for future memory and storage systems. In addition, the topic includes emerging memory devices and technologies (MRAM, FeFET, PCM, RRAM, OxRAM, memristive, molecular and quantum memories); memory-centric computing paradigms (processing-in-memory, computing-in-memory, logic-in-memory, neuromorphic computing, associative memories, hardware accelerators, and AI-native memory architectures); heterogeneous and 3D-integrated memory systems; memory technologies for edge, cloud, and high-performance computing; and techniques for reliability, security, sustainability, variability, endurance, and runtime management of future memory hierarchies.

      Chair: Moritz Fieback, Delft University of Technology, NL

      Co-Chair: Sonal Shreya, Aarhus University, DK

      Topic Members

      • Laura Bégon-Lours, ETH Zürich, CH
      • Tim Boehnert, International Iberian Nanotechnology Laboratory (INL), PT
      • Erika Covi, Technical University of Munich, DE
      • Seema Dhull, Principal Engineer, IN
      • Farshad Firouzi, ASU, US
      • Anteneh Gebregiorgis, Delft University of Technology, NL
      • Gaurav Kumar K, Nvidia Corporation, US
      • Wantong Li, University of California, Riverside, US
      • Piergiulio Mannocci, Unconventional AI, US
      • Fanfan Meng, Imec, BE
      • Arshid Nisar, Department of Electronics and Communication Engineering, National Institute of Technology Srinagar, IN
      • Vasilis Ntinas, Aalborg University, DK
      • William Simon, IBM Research Europe - Zurich, CH
      • Ken Takeuchi, The University of Tokyo, JP
      • Kanishkan Vadivel, IMEC Netherlands, NL
      • Xueyan Wang, Beihang University, CN
      • Tianyao Xiao, Sandia National Laboratories, US

      D16 Design Automation for Quantum Computing

      This topic focuses on design methods and software for quantum and hybrid quantum-classical architectures; compilation, mapping and synthesis methods for quantum circuits; quantum error correction and error mitigation in quantum systems; design and performance evaluation of NISQ and beyond algorithms and applications; quantum technologies and hardware architectures; simulation, verification, reliability, test, design of full-stack quantum computing systems and cross-layer methodologies for NISQ and scalable modular fault-tolerant architectures; hardware-software co-design; cryo-CMOS control electronics.

      Chair: Ilia Polian, University of Stuttgart, DE

      Co-Chair: Carmen G. Almudever, Technical University of Valencia, ES

      Topic Members

      • Michele Amoretti, University of Parma, IT
      • Sebastian Brandhofer, IBM Quantum, DE
      • Lukas Burgholzer, Technical University of Munich, DE
      • Kamalika Datta, University of Bremen, DE
      • Michael Epping, German Aerospace Center (DLR), DE
      • Sebastian Feld, Delft University of Technology, NL
      • Francisco Garcia-Herrero, Universidad Complutense de Madrid, ES
      • Edoardo Giusto, University of Naples, Federico II, IT
      • Eneet Kaur, Cisco, US
      • Abhoy Kole, DFKI GmbH, DE
      • Siyuan Niu, University of Central Florida, US
      • Alexandru Paler, Aalto University, FI
      • Jennifer Paykin, Galois, Inc, US
      • Daniel Scherer, Fraunhofer IIS, DE
      • Quentin Schmidt, Technische Universiteit Delft, NL
      • Michal Stechy, PsiQuantum, PL
      • Aida Todri-Sanial, Eindhoven University of Technology, NL

      Track A: Application Design

      A1 Power-efficiency, Smart Energy Systems and Life Cycle Optimization for Sustainable Computing

      Application design experiences and real-world implementations of power-efficient systems, smart energy management approaches across scales, life cycle optimization approaches, or minimized environmental impact circuits with high industrial relevance, especially targeting ultra-low-power, high-performance, or large-scale computing systems and related Internet-of-Things/Cyber-Physical applications for sustainable computing (such as MPSoCs, mobile systems, massively parallel computers, 2D/3D multi-/many-core systems, high-performance computing clusters, data centres, and cloud systems).

      Chair: Maxime Pelcat, IETR-INSA, FR

      Co-Chair: Nikela Papadopoulou, University of Glasgow, GB

      Topic Members

      • Eishi Arima, Technical University of Munich, DE
      • Jing Chen, Chalmers University of Technology, SE
      • Andreas Diavastos, National University of Singapore, SG
      • Orlando Moreira, GrAI Matter Labs, NL
      • Jisung Park, POSTECH (Pohang University of Science and Technology), KR
      • Sébastien Rumley, HES-SO // HEIA-Fribourg, CH

      A2 Smart Society and Digital Wellness

      Design experiences, practical applications, optimization, and real-life implementations of software, devices, systems, and services, from the Edge to the Cloud, for smart cities, smart homes and people wellness, based on mass market electronics, Internet of Things (IoT), Internet of Medical Things (IoMT), and Internet-of-Everything (IoE). This encompasses a diverse array of subjects, ranging from the development and deployment of advanced technologies to their seamless integration into modern everyday life by means of a variety of AI-powered smart devices and intelligent systems with sensing and acting capabilities, which are adopted in different sectors: from individual’s social care and healthcare to home automation and management of urban infrastructures. Topics of interests include, but are not limited to, the design, the optimization and the application of sensors, sensor networks, wearables, smart devices, cyberphysical and robotic systems for smart home, smart cities, and people wellness, including augmented and assisted living, social care products, healthcare devices, technologies and services for disease’s prevention, diagnosis, treatment and rehabilitation, smart transportation, environmental monitoring, resources’ supply and management (e.g., water, air, energy, etc.), lighting, street cleaning, disposal facilities, etc. including also the use of security-privacy techniques and blockchain technology, 5G and 6G mobile communications, networking devices, audio and video technologies, and advanced human-machine interfaces.

      Chair: Tiziana Margaria, University of Limerick and Lero, IE

      Co-Chair: Florenc Demrozi, Department of Electrical Engineering and Computer Science, University of Stavanger, NO

      Topic Members

      • Christophe Bobda, University of Florida, US
      • Baibhab Chatterjee, University of Florida, US
      • Bahar Farahani, Shahid Beheshti University, IR
      • Mohammad Hamad, Technical University of Munich, DE
      • Salvatore Tedesco, University College Cork, IE
      • Cristian Turetta, Wenzhou Business College, CN
      • Federica Zonzini, University of Bologna, IT

      A3 Secure Systems, Circuits and Architectures

      Focus on secure systems, circuits, and architectures, with an emphasis on design experiences, real-world deployments, applications, and silicon prototypes. Topics of interest include: secure hardware architectures; hardware/software implementations for post-quantum embedded cryptography (e.g., post-quantum, lightweight, homomorphic); emerging technologies for secure system design; novel architectures for embedded cryptography; demonstrations of physical attacks (e.g., fault injection, side-channel) and countermeasures; embedded processors and co-processors for security; protection of off-chip memory; secure Network-on-Chip communication and integrity; hardware-enabled security demonstrated on real systems or prototypes; logic-level security; firmware security.

      Chair: Mirjana Stojilovic, EPFL, CH

      Co-Chair: Jo Vliegen, ES&S, COSIC, ESAT, KU Leuven, BE

      Topic Members

      • Levent Aksoy, Tallinn University of Technology, EE
      • Manaar Alam, New York University Abu Dhabi, AE
      • Lilas Alrahis, Khalifa University, AE
      • Alejandro Cabrera Aldaya, Tampere University, FI
      • Luca Cassano, Politecnico di Milano, IT
      • Anastasija Collen, University of Applied Sciences and Arts of Western Switzerland, CH
      • Dennis Gnad, Karlsruhe Institute of Technology (KIT) and Expected IT GmbH, DE
      • Matthias Hiller, Fraunhofer AISEC, DE
      • Wei Hu, Northwestern Polytechnical University, CN
      • Mounia Kharbouche-Harrari, STMicroelectronics, FR
      • Suparna Kundu, COSIC, KU Leuven, BE
      • Honorio Martin, University Carlos III of Madrid, ES
      • Maria Mendez Real, Lab-STICC CNRS UMR 6285, FR
      • Roman Pletka, IBM Research, CH
      • Amin Rezaei, California State University, Long Beach, US
      • Erkay Savas, Sabanci University, TR

      A4 Autonomous Systems and Smart Industry

      This topic focuses on self-adaptive, learning, and/or context-aware systems with run-time decision-making capabilities for smart sensing, intelligent actuation, autonomous operation, and efficient computing/communication across diverse application domains, including emerging smart industry scenarios. It targets the compute continuum, covering high-performance compute nodes, power-constrained IoT/edge devices, reconfigurable systems, and heterogeneous/collaborative platforms. Optimization goals involve computing performance, energy/power, reliability, temperature, aging, or quality. Topics of interest include but are not limited to: Adaptive strategies for run-time resource management; Prediction/forecasting and control of self-adaptive systems; Systems and/or algorithms that can adapt their operation based on available resources and context; Data mining, modelling, and optimization techniques for adaptive systems (e.g. control automation and game theory.); Automotive; Autonomous Driving; Mobile Robotics; Human-Robot collaborations in smart factories; Industry 4.0 and 5.0; Digital Twins; Virtualization; Metaverse; 5G/6G; MEMS; Integrated sensors and transducers; Design experiences and industrial use-cases of self-adaptive systems.

      Chair: Antonio Miele, Politecnico di Milano, IT

      Co-Chair: Heba Khdr, Karlsruhe Institute of Technology (KIT), DE

      Topic Members

      • Iraklis Anagnostopoulos, Southern Illinois University Carbondale, US
      • Yuting Fu, NXP Semiconductors, NL
      • Sebastiano Gaiardelli, Technical University of Munich, DE
      • Zain A. H. Hammadeh, German Aerospace Center (DLR), DE
      • Seonyeong Heo, Kyung Hee University, KR
      • Anil Kanduri, University of Turku, FI
      • Geoff Merrett, University of Southampton, GB
      • Paolo Pazzaglia, Robert Bosch GmbH, DE
      • Antonio Carlos Schneider Beck, Universidade Federal do Rio Grande do Sul, BR

      A5 Applications of Emerging Technologies

      Applications of and design methods for systems based on future and emerging technologies. Topics of interest include: neuromorphic and bio-inspired computing systems; bio-MEMS and lab-on-a-chip; emerging models of computation (e.g., quantum computing, reversible logic, approximate computing, stochastic computing); application case studies for emerging technologies (e.g., cryptography, wearable computing, e-textiles, energy-critical systems, etc.); photonic and optoelectronic computing; memristive and memcapacitive systems; hybrid classical-quantum architectures; analogue in-memory computing; brain-inspired edge AI; molecular and chemical computing; AI-assisted materials discovery for computing devices; spintronic and skyrmionic computing; carbon nanotube based circuit and architecture design; atom-based computing platforms; quantum networking and quantum internet protocols; energy-autonomous embedded systems; sustainable and green computing technologies.

      Chair: Guillermo Botella, Complutense University of Madrid, ES

      Co-Chair: Nazek El-Atab, MMH Labs, King Abdullah University of Science and Technology, Saudi Arabia, SA

      Topic Members

      • Pratishtha Agnihotri, Arizona State University, US
      • Carlos Cano, University of Granada, ES
      • Yuanqing Cheng, Beihang University, CN
      • Saptarshi Das, Pennsylvania State University, US
      • Ghada Dushaq, New York University Abu Dhabi, AE
      • José L. Imaña, Complutense University of Madrid, ES
      • Felipe Magalhaes, Ecole Polytechnique de Montreal, CA
      • Alberto Marchisio, New York University Abu Dhabi (NYUAD), AE
      • Shinobu Miwa, The University of Electro-Communications, JP
      • M. Hassan Najafi, Case Western Reserve University, US
      • Ratko Pilipović, University of Ljubljana, Faculty of Computer and Information Science, SI

      A6 Applications of Artificial Intelligence Systems

      Advanced technologies and systems, software, algorithmic and co-design approaches and optimizations for artificial intelligence (AI), machine learning and deep learning solutions for domain-specific applications in the context of computing continuum and embodied AI: from resource-constrained edge devices (for example machine learning on microcontrollers and low-power processors embedded in mobile and/or autonomous systems) up to high-performance computing in the cloud and their applications. Topics of interests include Computer Vision, Natural Language Processing, Generative AI, Large Language Models, Large Vision Models, Vision-Language Models, Few-Shot Learning, Continual Learning, Distributed and Federated AI, Robust AI, Real-Time and Adaptive Inference, Quantization and Pruning, Neural Architecture Search.

      Chair: Kuan-Hsun Chen, University of Twente, NL

      Co-Chair: Sercan Aygun, University of Louisiana at Lafayette, US

      Topic Members

      • Hiromitsu Awano, Nagoya University, JP
      • Jona Beysens, KU Leuven, BE
      • Joao Paulo Cardoso de Lima, TU Dresden, DE
      • Thomas Chau, Samsung AI Center, GB
      • Shuo-Han Chen, National Yang Ming Chiao Tung University, TW
      • Tianyue Chu, Telefonica Research, ES
      • Bruno Endres Forlin, University of Twente, NL
      • Dr. G.A. Gillani, University of Twente, NL
      • Christian Hakert, TU Dortmund, DE
      • Chien-Chung Ho, National Cheng Kung University, TW
      • Joonsung Kim, Sungkyunkwan University, KR
      • Masaaki Kondo, Keio University, JP
      • Qiao Li, Mohamed bin Zayed University of Artificial Intelligence, AE
      • Shengzhong Liu, Shanghai Jiao Tong University, CN
      • Xiaoli Liu, University of Helsinki, FI
      • Dongning Ma, MBZUAI, AE
      • Giulio Masinelli, CSEM, CH
      • Vojtech Mrazek, Brno University of Technology, CZ
      • Vinod Nigade, eBay Amsterdam, NL
      • Veljko Pejovic, University of Ljubljana, SI
      • Farzad Razi, University of Minnesota, US
      • Jože Rožanec, Jožef Stefan Institute, SI
      • Purab Sutradhar, Boise State University, US
      • Sepehr Tabrizchi, University of Illinois Chicago, US
      • Giuseppe Tagliavini, University of Bologna, IT
      • Mahdi Taheri, BTU Cottbus, DE
      • Guangzhi Tang, Maastricht University, NL
      • Mohamed Wahib, RIKEN, JP
      • Lei Xun, Imperial College London, GB
      • Mikail Yayla, Ruhr University Bochum, DE
      • Hanting Ye, Duke University, US
      • Kasim Sinan Yildirim, University of Trento, IT

      Track T: Test and Dependability

      T1 Modelling and mitigation of defects, faults, variability, and reliability

      Identification, characterization, and modelling of defects, faults, and degradation mechanisms in conventional, advanced, or emerging technologies (FinFET, FDSOI, TSV, Memristor, MTJ, CNT, etc.); defect-based fault analysis; reliability assessment and modelling at device, or circuit level; process yield modelling and enhancement; design-for-manufacturability, design-for-yield and design-for-reliability; noise and uncertainty modelling at device or circuit level; modelling and mitigation of physical sources of faults and errors such as process, voltage, temperature and temporal variations at device or circuit level.

      Chair: Arnaud Virazel, LIRMM, FR

      Co-Chair: Cristina Meinhardt, UFSC, BR

      Topic Members

      • Jaume Abella, Barcelona Supercomputing Center (BSC-CNS), ES
      • Mohammad Hasan Ahmadilivani, Tallinn University of Tehnology, EE
      • Sarah Azimi, Politecnico di Torino, IT
      • Riccardo Cantoro, Politecnico di Torino, IT
      • Bastien Deveautour, Nantes University - IETR, FR
      • Eric Faehn, STMicroelectronics, FR
      • Naghmeh Karimi, University of Maryland Baltimore County, US
      • Rene Krenz-Baath, TH-Wildau, DE
      • Huawei Li, Institute of Computing Technology, Chinese Academy of Sciences, CN
      • Lirida Naviner, Télécom Paris, FR
      • Jaan Raik, Tallinn University of Technology, EE
      • Sourjya Roy, Purdue University, US
      • Ernesto Sanchez, Politecnico di Torino, IT
      • Christian Sauer, Synopsys, DE
      • Hank Walker, Texas A&M University, US
      • Xiaoqing Wen, Kyushu Institute of Technology, JP

      T2 Test generation, test architectures, design for test, and diagnosis

      Automated test pattern generation targeting basic and advanced fault models (timing-related, defect-based, cell-aware) in a wide range of semiconductor digital integrated circuits including microprocessors, SoC, FPGAs, memories, NoCs, accelerators, hardware for machine learning and artificial intelligence, 2.5D and 3D architectures; silent data corruption; fault simulation; power and thermal issues in test; design for testability (DFT); test compression; multi-corner stress tests; volume fault diagnosis and yield analysis; logic built-in self-test (BIST) and memory BIST; in-system test; board and system-level test; test scheduling; machine learning and artificial intelligence in IC testing.

      Chair: Annachiara Ruospo, Politecnico di Torino, IT

      Co-Chair: Melanie Schillinsky, NXP Germany GmbH, DE

      Topic Members

      • Atefe Dalirsani, Bosch Semiconductors, DE
      • Stephan Eggersgluess, Siemens EDA, DE
      • Sybille Hellebrand, Paderborn University, DE
      • Stefan Holst, Kyushu Institute of Technology, JP
      • Yu Huang, HiSilicon, US
      • Maria K. Michael, Electrical and Computer Engineering & KIOS Center of Excellence, University of Cyprus, CY
      • Frank Poehl, FP Consulting, DE
      • Haralampos-G. Stratigopoulos, Sorbonne University, CNRS, LIP6, FR
      • Jerzy Tyszer, Poznan University of Technology, PL
      • Thilo Wagner, Racyics GmbH, DE

      T3 System and Cross-layer Dependability and Test

      As computing systems evolve - from embedded and edge devices to large-scale cloud and HPC infrastructures - ensuring reliability, safety, and fault tolerance is critical, especially in the hardware platforms required to deploy modern AI models. This topic focuses on approaches spanning hardware and software stacks, from microarchitecture to system-level design, with particular attention to hardware-originated faults and their impact on the whole stack. The scope includes reliability, safety, and test, with a focus on cross-layer fault modeling and reliability assessment, run-time verification and management, monitoring, recovery, mitigation, and adaptive/reconfigurable approaches. We particularly welcome contributions addressing the design, validation, and operation of hardware substrates for AI workloads. Contributions may combine theoretical insights with practical solutions for building dependable, safe, energy-efficient, and testable systems across the computing spectrum. Relevant topics include, but are not limited to, high-level synthesis, microarchitectures, runtime and system software, approximate computing, hardware-aware AI deployment, accelerator reliability, workload mapping, fault-tolerant inference and training, and resilient memory and interconnect subsystems. Emerging failure modes and silent data corruption are also considered, especially at scale and in AI-intensive deployments, together with strategies for recovery, redundancy, monitoring, survivability, and graceful degradation across all segments, including cloud, edge, and embedded systems.

      Chair: Stefano Di Carlo, Politecnico di Torino, IT

      Co-Chair: Angeliki Kritikakou, Univ Rennes, Inria, CNRS, IRISA, FR

      Topic Members

      • Cristiana Bolchini, Politecnico di Milano, IT
      • Ramon Canal, Universitat Politècnica de Catalunya, ES
      • Fernando Fernandes dos Santos, INRIA, FR
      • Yanjing Li, Northeastern University, US
      • Gabriel Luca Nazar, Universidade Federal do Rio Grande do Sul, BR
      • George Papadimitriou, University of Patras, GR
      • Salvatore Pappalardo, Ecole Centrale de Lyon, FR

      DT4 Design and test for analogue and mixed-signal circuits and systems, and MEMS

      Analogue, radio-frequency, mixed-signal, MEMS, circuit and system synthesis and optimization; layout and parasitic-aware synthesis; design for manufacturability, yield, reliability; analysis of variability effects; performance modelling; formal, numerical and symbolic simulation methods; topology generation; HW description languages and models of computation; self-healing and self-calibration; test generation, built-in self-test and design for testability; fault modelling, diagnosis and simulation; defect characterization and failure analysis; on-line test and fault tolerance; test metrics.

      Chair: Ricardo Martins, Instituto de Telecomunicações / Instituto Superior Técnico – Universidade de Lisboa, PT

      Co-Chair: Salvador Mir, CNRS/Univ. Grenoble Alpes/TIMA, FR

      Topic Members

      • Martin Andraud, UCLouvain, BE
      • Tiago Balen, UFRGS, BR
      • Manuel Barragan, TIMA Laboratory, FR
      • Hung-Ming Chen, Institute of Electronics, National Yang Ming Chiao Tung University, TW
      • Chenhao Chu, ETH Zurich, CH
      • William Eisenstadt, University of Florida, US
      • Renato Feitoza, PROPHESEE, FR
      • Husni Habal, Infineon Technologies AG, DE
      • Lida Kouhalvandi, Dogus university, TR
      • Yolanda Lechuga, University of Cantabria, ES
      • Piero Malcovati, University of Pavia, IT
      • Juho Park, Princeton Univerrsity, US
      • Fabio Passos, University of Lisbon and INESC-ID, PT
      • Elisenda Roca, Instituto de Microelectronica de Sevilla, ES
      • Rosa Rodríguez-Montañés, UPC, ES
      • Armin Tajalli, University of Utah, US
      • Yasuhiro Takashima, University of Kitakyushu, JP

      DT5 Design and test of hardware security primitives

      Hardware security primitives, including classical and post-quantum cryptographic circuits, multiparty computation (MPC), zero-knowledge proof systems, homomorphic encryption; side-channel countermeasure primitives and analysis (including modelling, verification, and simulation); fault injection countermeasures and attacks; physically unclonable functions (PUF) and true random number generators (TRNG); hardware trojan primitives; AI methods in hardware security; AI accelerators and their relevant physical attacks and countermeasures; nano security primitives.

      Chair: Paolo Maistri, TIMA Laboratory, FR

      Co-Chair: Lukasz Chmielewski, Masaryk University (Brno, Czechia), CZ

      Topic Members

      • Aydin Aysu, North Carolina State University, US
      • Gaëtan Cassiers, UCLouvain, BE
      • Elke De Mulder, Google, US
      • Wieland Fischer, Infineon Technologies, DE
      • Sylvain Guilley, Secure-IC, FR
      • Xiaolu Hou, Nanyang Technological University, SG
      • Tuba Kiyan, Technische Universität Berlin, DE
      • Maurizio Martina, Politecnico di Torino, IT
      • Philippe Maurine, University of Montpellier, FR
      • Silvia Mella, Radboud University, NL
      • Athanasios Papadimitriou, Department of Digital Systems, University of the Peloponnese, GR
      • Michael Pehl, Technical University of Munich, DE
      • Marta Portela-Garcia, Universidad Carlos III de Madrid, ES
      • Markku-Juhani Saarinen, Tampere University, FI
      • Julian Speith, Max Planck Institute for Security and Privacy (MPI-SP), DE
      • Dilara Toprakhisar, KU Leuven, BE
      • Rei Ueno, Kyoto University, JP
      • Praveen Vadnala, PQShield BV, NL
      • Emanuele Valea, CEA LIST, FR
      • Raphael Viera, Mines Saint-Etienne, FR
      • Srinivas Vivek, IIIT Bangalore, IN

      DT6 Design and test of secure systems

      Design-for-trust (secure design methods); Design, test, verification and automation for side-channel, fault attacks and countermeasures for cryptographic systems (lightweight, symmetric, public-key, post-quantum); Microarchitectural attacks; Test infrastructure for secure devices; Trusted manufacturing; Counterfeit detection and avoidance; HW tampering (attacks, detection, or countermeasures); HW trojans (attacks, detection, or countermeasures); Machine learning for any of the above topics including attacks, detection, or countermeasures.

      Chair: Tobias Schneider, NXP Semiconductors, AT

      Co-Chair: Ileana Buhan, Radboud University, NL

      Topic Members

      • Anita Aghaie, Siemens AG, DE
      • Tolga Arul, Barkhausen Institut, DE
      • Jakub Breier, TTControl GmbH, AT
      • Anupam Chattopadhyay, Nanyang Technological University, SG
      • Ricardo Chaves, INESC-ID, IST, Universidade de Lisboa, PT
      • Giorgio Di Natale, TIMA - CNRS, FR
      • Nisha Jacob Kabakci, Fraunhofer AISEC, DE
      • Dirmanto Jap, Temasek Laboratories @NTU, SG
      • Dina Kamel, Universit� catholique de Louvain, BE
      • ayesha khalid, Queen's University Belfast, GB
      • Johann Knechtel, New York University Abu Dhabi, AE
      • Georg Land, Intel, DE
      • Vianney Lapotre, Univ. Bretagne Sud, UMR CNRS 6285, Lab-STICC, FR
      • Itamar Levi, Faculty of Engineering, Bar-Ilan University, IL
      • Soundes Marzougui, Qubit Guard, DE
      • David Oswald, Durham University, GB
      • Kostas Papagiannopoulos, University of Amsterdam, NL
      • Francesco Regazzoni, University of Amsterdam and Università della Svizzera italiana, CH
      • Aein Rezaei Shahmirzadi, PQShield, DE
      • Junko Takahashi, NTT Social Informatics Laboratories, JP
      • Lichao Wu, University of Bristol, GB

      Track E: Embedded Systems Design

      E1 Embedded software architecture, compilers and tool chains

      Software architectures, programming paradigms, languages, compiler support, software tools, and techniques (e.g., simulators, synthesis tools) targeting embedded heterogeneous systems for domain-specific applications such as IoTs and wearables; embedded software support for approximate computation and FPGA/GPU based accelerators; memory communication protocols and hierarchy management, including caches, scratchpad, and non-volatile memories; code analysis, code optimization/generation to enhance performance, power/energy, code/data size, reliability, security, distributed system software, virtualization, and middleware for embedded systems, including resource-awareness, reconfiguration, energy/power management; compiler support for enhanced debugging, profiling, and traceability.

      Chair: Michele Lora, University of Verona, IT

      Co-Chair: Sara Royuela, Barcelona Supercomputing Center, ES

      Topic Members

      • João Bispo, Faculty of Engineering (FEUP), University of Porto, PT
      • Luigi Capogrosso, Interdisciplinary Transformation University of Austria, AT
      • Jeronimo Castrillon, TU Dresden, DE
      • Li-Pin Chang, National Yang Ming Chiao Tung University, TW
      • Urbi Chatterjee, Indian Institute of Technology Kanpur, IN
      • Mickaël Dardaillon, Univ Rennes, INSA Rennes, CNRS, IETR - UMR 6164, FR
      • Raul de la Cruz, Collins Aerospace, IE
      • David Gregg, Trinity College Dublin, IE
      • Frank Hannig, Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), DE
      • Ann Franchesca Laguna, De La Salle University, PH
      • claire pagetti, ONERA, FR
      • Shubham Rai, Robert Bosch Research GmbH, DE
      • Konstantinos Sagonas, Uppsala University & Nat. Tech. Univ, of Athens, SE
      • Martin Schoeberl, Technical University of Denmark, DK
      • Chin-Hsien Wu, Department of Electronic and Computer Engineering, National Taiwan University of Science and Technology, TW

      E2 Real-time and dependable systems

      Real-time performance modelling, analysis and empirical evaluation; worst-case performance analysis techniques; WCET analysis techniques, real-time schedulability of multicore systems; use of hardware virtualization techniques in time-critical applications; power-aware real-time systems; industrial case studies of real-time systems, networked and dependable systems; adaptive real-time systems; dependable real-time systems including fault-tolerance and criticality; timing analysis of security attack protection and privacy-enhancement in time-critical systems; network control and QoS for embedded applications; resource allocation and design-space exploration for real-time embedded systems; time-critical distributed systems; time-critical IoT; real-time edge and cloud computing; use of ML for real-time scheduling and analysis.

      Chair: Irem Boybat, IBM Research Europe - Zurich, CH

      Co-Chair: Angelo Garofalo, University of Bologna, ETH Zurich, IT

      Topic Members

      • Andrea Baldovin, Infineon, IT
      • Anais FINZI, TTTech Computertechnik AG, AT
      • Emmanuel Grolleau, LIAS, ISAE-ENSMA, Universite de Poitiers, FR
      • Tanja Harbaum, KIT, DE
      • Lisa Maile, Eindhoven University of Technology (TU/e), NL
      • Patrick Meumeu Yomsi, CISTER Research Centre, ISEP, Polytechnic Institute of Porto, PT
      • Guillermo Rodriguez-Navas, Nokia Bell Labs, IL
      • Jean-Luc Scharbarg, Université de Toulouse - IRIT/ENSEEIHT/INPT, FR
      • Yue Tang, Northeastern University, CN
      • Alexander Zuepke, Technical University of Munich, DE

      E3 Machine learning solutions for embedded and cyber-physical systems

      Hardware architectures, software and algorithmic approaches for embedded and edge artificial intelligence & machine learning, including deep learning, generative AI, and neuromorphic systems; specialized, heterogeneous, and resource-efficient embedded architectures for machine learning; resource-constrained embedded architectures and software for autonomy, automated reasoning, and planning algorithms; software frameworks, compilers, and techniques for deployment of ML/AI on embedded and cyber-physical devices; embedded, cyber-physical, and robotic systems exploiting edge machine learning and AI solutions; hardware/software solutions for embedded AI and machine learning in mixed-criticality systems for automotive, space, and other applications.

      Chair: Irem Boybat, IBM Research Europe - Zurich, CH

      Co-Chair: Angelo Garofalo, University of Bologna, ETH Zurich, IT

      Topic Members

      • Amir Aminifar, Lund University, SE
      • Oliver Bringmann, University of Tübingen / FZI, DE
      • Alessio Burrello, Politecnico di Torino and Università di Bologna, IT
      • Alessandro Capotondi, Universita' di Modena e Reggio Emilia, IT
      • Alessandro Cilardo, University of Naples Federico II, IT
      • Antonio De Vita, STMicroelectronics, IT
      • Lev Denisov, Politecnico di Milano, IT
      • Chao Fang, KU Leuven, BE
      • Maryam Hemmati, University of Auckland, NZ
      • Darong Huang, The University of Hong Kong (HKU), HK
      • Daniele Jahier Pagliari, Politecnico di Torino, IT
      • Rafael Medina Morillas, ETH Zurich, CH
      • Pietro Mercati, Intel, US
      • Jose Miranda, UPM, ES
      • Işıl Öz, Izmir Institute of Technology, TR
      • Ozcan Ozturk, Sabanci University, TR
      • Flavio Ponzina, San Diego State University, US
      • Alfonso Rodriguez, Universidad Politecnica de Madrid, ES
      • Manuele Rusci, KU Leuven, BE
      • Enrico Russo, University of Catania, IT
      • Mohammad Sadrosadati, ETH Zurich, CH
      • Dolly Sapra, University Van Amsterdam, NL
      • Giuseppe Sarda, Mosaic SoC, SZ
      • Jiawei Xu, University of Macau, MO
      • Xiaofan Yu, University of California Merced, US

      E4 Design methodologies for machine learning architectures

      Design methodologies, optimizations, verification, analysis and reliability for machine learning architectures; Specializations, and resource-efficient optimizations for machine learning architectures; Embedded architectures and software for autonomy, automated reasoning, and planning algorithms; Approximate architectures for machine learning applications; Learning from limited data sets; Frameworks for probabilistic and deep learning programming; Safe and secure machine learning; novel neural networks architectures and concepts for embedded computing; In-memory and near-memory architectures design for ML; Hyperdimensional computing architectures and ML applications; Quantum computing for ML; Co-design space exploration for ML applications.

      Topic Members

        E5 Design, specification, modelling and verification for embedded and cyber-physical systems

        Modelling, design, verification, validation and optimization of complex, heterogeneous, distributed Cyber-Physical Systems (CPS); specification and analysis of functional and non-functional properties, including performance, timing, memory usage, quality-of-service, safety and reliability; meta-models and models of computation, communication, and concurrency for complex HW-SW systems and components of CPS; theories, standards, languages and tools supporting model-based design flows covering software, control, and physical components; verification techniques ranging from simulation, testing, model-checking, SAT and SMT-based reasoning, compositional analysis and analytical methods as well as monitoring and runtime verification; data-mining, autonomy, and adaptivity in CPS, networked and switched control systems (e.g. control/architecture co-design and architecture-aware controller synthesis); cognitive control for CPS and socio-technical systems (e.g. empowered consumer and organizational behaviour in smart grids); predictive and learning-based models for CPS.

        Chair: Chung-Wei Lin, National Taiwan University, TW

        Co-Chair: Gianluca Palermo, Politecnico di Milano, IT

        Topic Members

        • Christian Haubelt, University of Rostock, DE
        • Chadlia Jerad, University of Manouba, TN
        • BaekGyu Kim, DGIST, KR
        • Hokeun Kim, Arizona State University, US
        • Frederic Mallet, Universite Cote d'Azur, FR
        • Francesca Palumbo, University of Cagliari, IT
        • Georgios L. Stavrinides, KIOS Research and Innovation Center of Excellence, University of Cyprus, CY
        • Todor Stefanov, Leiden University, NL